QNLP  v1.0
test_bit_group.cpp
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1 
11 //#define CATCH_CONFIG_RUNNER
12 //#define CATCH_CONFIG_MAIN
13 
14 #include "catch2/catch.hpp"
15 #include "Simulator.hpp"
16 #include "IntelSimulator.cpp"
17 #include <memory>
18 #include "bit_group.hpp"
19 
20 using namespace QNLP;
21 #include <bitset>
22 
27 TEST_CASE("Test bit grouping","[bitgroup]"){
28  std::size_t num_qubits = 8;
29  std::vector<std::size_t> reg, aux;
30  for (int i = 0; i < num_qubits; i++){
31  if(i < num_qubits-2){ reg.push_back(i); }
32  else{ aux.push_back(i); }
33  }
34  std::cout << reg.size() << " | "<< aux.size() << std::endl;
36  BitGroup<decltype(sim)> bg;
37  auto& r = sim.getQubitRegister();
38  /*
39  SECTION("Group to right |010100>|10> -> |000011>|10>"){
40  sim.initRegister();
41  sim.applyGateX(reg[1]);
42  sim.applyGateX(reg[3]);
43 
44  sim.applyGateX(aux[0]);
45  bg.bit_swap_s2e(sim, reg, aux);
46 
47  sim.PrintStates("Post");
48  }*/
49  SECTION("Group to right |010000>|10> + |011000>|10> -> |000001>|10> + |000011>|10>"){
50  sim.initRegister();
51  sim.applyGateX(reg[1]);
52  sim.applyGateH(reg[2]);
53 
54  sim.applyGateX(aux[0]);
55  bg.bit_group(sim, reg, aux, true);
56 
57  sim.PrintStates("PostSuper");
58  }
59 
60 }
61 
62 // 1.00000000 + i * 0.00000000 % |100110> p=1.000000
63 // 1.00000000 + i * 0.00000000 % |110010> p=1.000000
Class definition for IntelSimulator. The purpose of this class is to map the functionality of the und...
static void bit_group(SimulatorType &qSim, const std::vector< std::size_t > &qreg_idx, const std::vector< std::size_t > &qaux_idx, bool lsb=true)
Swaps all qubits in register indices given by qreg_idx to their right-most positions....
Definition: bit_group.hpp:114
Class definition for bit-wise grouping in register.
Definition: bit_group.hpp:25
TEST_CASE("Test bit grouping","[bitgroup]")
Test BitGroup.
Implements grouping of bits to LSB side of register.