QNLP  v1.0
test_bin_into_superpos.cpp File Reference
#include "bin_into_superpos.hpp"
#include "Simulator.hpp"
#include "IntelSimulator.cpp"
#include "catch2/catch.hpp"
#include <bitset>
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Typedefs

typedef ComplexDP Type
 

Functions

 TEST_CASE ("Test encoding of binary (integers) to superposition","[encode]")
 Test binary encoding basic implementation. More...
 
 TEST_CASE ("Test encoding of different register sizes and checking states' amplitudes","[encode_amp]")
 Test binary encoding for different register sizes and checking that the states' amplitudes are correct. More...
 

Typedef Documentation

◆ Type

typedef ComplexDP Type

Definition at line 13 of file test_bin_into_superpos.cpp.

Function Documentation

◆ TEST_CASE() [1/2]

TEST_CASE ( "Test encoding of binary (integers) to superposition"  ,
""  [encode] 
)

Test binary encoding basic implementation.

Definition at line 21 of file test_bin_into_superpos.cpp.

21  {
22  SECTION("Testing qubit encoding"){
23 
24  std::size_t num_qubits = 10;
25 
26  std::size_t len_reg_memory = (num_qubits - 2) / 2;
27  std::size_t len_reg_auxiliary = len_reg_memory + 2;
28  std::size_t num_bin_pattern = pow(2,len_reg_memory) - 2;
29 
31  sim.initRegister();
32 
33  REQUIRE(sim.getNumQubits() == num_qubits);
34 
35  // Set up registers to store indices
36  std::vector<std::size_t> reg_memory(len_reg_memory);
37  for(std::size_t i = 0; i < len_reg_memory; i++){
38  reg_memory[i] = i;
39  }
40  std::vector<std::size_t> reg_auxiliary(len_reg_auxiliary);
41  for(std::size_t i = 0; i < len_reg_auxiliary; i++){
43  }
44 
45  // Init data to encode
46  std::vector<std::size_t> vec_to_encode(num_bin_pattern);
47  for(std::size_t i = 2; i < num_bin_pattern; i++){
48  vec_to_encode[i-2] = i;
49  }
50 
51  std::size_t val;
52  // Encode
54  encoder.encodeBinInToSuperpos_unique(sim, reg_memory, reg_auxiliary, vec_to_encode);
55 
56  // Measure
57  val = sim.applyMeasurementToRegister(reg_memory);
58 
59  CHECK_THAT(vec_to_encode, VectorContains(val));
60  }
61 }
Class definition for IntelSimulator. The purpose of this class is to map the functionality of the und...
Definition of class to encode a binary string represented by an integer into a superposition of state...

References QNLP::EncodeBinIntoSuperpos< SimulatorType >::encodeBinInToSuperpos_unique(), QNLP_Python_MPI::len_reg_auxiliary, QNLP_EndToEnd_MPI::len_reg_memory, QNLP_Python_MPI::num_bin_pattern, ncu_opt_tester::num_qubits, QNLP_Python_MPI::reg_auxiliary, QNLP_EndToEnd_MPI::reg_memory, ncu_opt_tester::sim, QNLP.tagging.tag_file::val, and QNLP_EndToEnd_MPI::vec_to_encode.

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◆ TEST_CASE() [2/2]

TEST_CASE ( "Test encoding of different register sizes and checking states' amplitudes"  ,
""  [encode_amp] 
)

Test binary encoding for different register sizes and checking that the states' amplitudes are correct.

Definition at line 67 of file test_bin_into_superpos.cpp.

67  {
68  const std::size_t max_qubits = 5;
69  double mach_eps = 7./3. - 4./3. -1.;
70 
71  std::size_t num_qubits;
72  std::size_t len_reg_auxiliary;
73  std::size_t num_bin_pattern;
74  std::size_t val;
75 
76  std::size_t test_pattern = 2;
77 
78  double expected_val;
79 
80  for(std::size_t len_reg_memory = 2; len_reg_memory < max_qubits; len_reg_memory++){
81  DYNAMIC_SECTION("Testing " << len_reg_memory << " memory qubits"){
82 
83  // Experiment set-up
84  num_qubits = 2*len_reg_memory + 2;
87 
88  // Expected real part of amplitude for equally encoded states
89  expected_val = sqrt(1.0 / (double) num_bin_pattern);
90 
92  sim.initRegister();
93  auto &r = sim.getQubitRegister();
94 
95  // Set up registers to store indices
96  std::vector<std::size_t> reg_memory(len_reg_memory);
97  for(std::size_t i = 0; i < len_reg_memory; i++){
98  reg_memory[i] = i;
99  }
100  std::vector<std::size_t> reg_auxiliary(len_reg_auxiliary);
101  for(std::size_t i = 0; i < len_reg_auxiliary; i++){
102  reg_auxiliary[i] = i + len_reg_memory;
103  }
104 
105  // Init data to encode
106  std::vector<std::size_t> vec_to_encode(num_bin_pattern);
107  for(std::size_t i = 0; i < num_bin_pattern; i++){
108  vec_to_encode[i] = i;
109  }
110 
111  // Encode
112  sim.encodeBinToSuperpos_unique(reg_memory, reg_auxiliary, vec_to_encode, len_reg_memory);
113 
114  for(int i = 0; i < num_bin_pattern; i++){
115  REQUIRE(r[i].real() + 10*mach_eps == Approx(expected_val).margin(1e-12));
116  REQUIRE(r[i].imag() + 10*mach_eps == Approx(0.).margin(1e-12) );
117 
118  }
119  for(int i = num_bin_pattern; i < pow(2,2*len_reg_memory); i++){
120  REQUIRE(r[i].real() + 10*mach_eps == Approx(0.).margin(1e-12));
121  REQUIRE(r[i].imag() + 10*mach_eps == Approx(0.).margin(1e-12) );
122  }
123  for(int i = pow(2,2*len_reg_memory); i < pow(2,2*len_reg_memory) + num_bin_pattern; i++){
124  REQUIRE(r[i].real() + 10*mach_eps == Approx(0.).margin(1e-12));
125  REQUIRE(r[i].imag() + 10*mach_eps == Approx(0.).margin(1e-12) );
126  }
127  for(int i = pow(2,2*len_reg_memory) + num_bin_pattern; i < pow(2,num_qubits); i++){
128  REQUIRE(r[i].real() + 10*mach_eps == Approx(0.).margin(1e-12));
129  REQUIRE(r[i].imag() + 10*mach_eps == Approx(0.).margin(1e-12) );
130  }
131 
132 
133  sim.collapseToBasisZ(reg_auxiliary[len_reg_auxiliary-2], 1);
134  val = sim.applyMeasurementToRegister(reg_memory);
135 
136  CHECK_THAT(vec_to_encode, VectorContains(val));
137 
138  }
139  }
140 }
Class definition for IntelSimulator. The purpose of this class is to map the functionality of the und...

References QNLP_Python_MPI::len_reg_auxiliary, QNLP_EndToEnd_MPI::len_reg_memory, QNLP_Python_MPI::num_bin_pattern, ncu_opt_tester::num_qubits, QNLP_Python_MPI::reg_auxiliary, QNLP_EndToEnd_MPI::reg_memory, ncu_opt_tester::sim, QNLP_EndToEnd_MPI::test_pattern, QNLP.tagging.tag_file::val, and QNLP_EndToEnd_MPI::vec_to_encode.